1. Field of the Invention
This invention relates to phase-locked loop frequency synthesizers and loop locking methods thereof, and more particularly, to a non-integer digitally phase-locked loop frequency synthesizer and a loop locking method thereof.
2. Description of Related Art
A phase-locked loop (PLL) is an electronic control system for generating a signal that has a constant ratio relative to a phase of a reference signal. The PLL synchronizes the frequency/phase of the reference signal and an output signal by using a feedback principle. When the PLL detects that the frequency/phase of the reference signal is changed, an internal feedback system adjusts the output signal (that is, adjusting the frequency of an oscillator), until the frequencies/phases of the signal output by the PLL and the reference signal are synchronous. In other words, the frequency/phase of the output signal can catch up with, or can be locked by, the frequency/phase of the reference signal.
The PLL may recover data and clock, modulate and demodulate frequencies and phases, and generate stable clock with multiplied frequency. Accordingly, the PLL is widely applied to various digital electronic instruments, consumer products, and communications devices such as a frequency synthesizer. According to the prior art, a PLL is usually implemented by an analog technique. However, in a deep submicron fabrication process, a traditional analog PLL has a low voltage headroom, and thus has a small tuning range. Thus, it is difficult to design a conventional analog PLL, and the PLL may not have a smaller area as the fabrication process advances. Therefore, it is difficult for the analog PLL to achieve the dual characteristics of fast phase locking and low noises.
In recent years, as the electronic element fabrication process made a significant progress, a digital circuit has more advantages than an analog circuit in performance and area. Regarding a conventional analog PLL, a concept of a digital oscillator is introduced to the art. The frequency of the oscillator is controlled by a digital signal, such that high oscillation rate and high resolution may be achieved. Accordingly, an all digital PLL applicable to an RF band is therefore realized. Taiwan Patent No. 400672 discloses a digital frequency synthesizer and a frequency synthesizing method thereof. The digital frequency synthesizer includes a frequency tracking unit, a pair of variable loop oscillators, and a clock control unit. The two oscillators act as clock signal outputs and provide a feedback signal to the frequency tracking unit. However, a higher frequency is difficult to be generated, because of the adoption of two frequency generators. Moreover, the two frequency generators, if not matching very well, may cause output frequency errors. Laid-open Taiwan Publication No. 200919976 discloses an all digital PLL that includes a digital loop filter and a modulator crossing the loop filter. The modulator includes an accumulator, an accumulation amplifier, and a route magnification device. A time-to-digital converter is used in a loop to detect a fractional part of a phase. However, the time-to-digital converter is complicated, and its resolution is easily affected by the fabrication process offset.
Note that for a convention phase-locked loop frequency synthesizer technique, in order to ensure system stability, a loop filter circuit 22 is realized by an integral route, which is realized by an integrator (composed of an adder 225 and a register 223), and a proportional route, as shown in FIG. 1, which shows a phase-locked loop frequency synthesizer according to the prior art. In the process that a loop is locked finally, an output of a phase/frequency detector 21 is sent to the loop filter circuit 22 for filtering, and then sent to the oscillator 23 for adjusting an output signal frequency fOUT. However, this technique, though solving the system stability problem, may generate great spurs on the output signal frequency fOUT. Such phenomenon is significant especially in a digitally phase-locked loop frequency synthesizer.
Compared with an analog circuit, a digital circuit still suffers from quantization noises, and quantification errors. Additionally, in a conventional non-integer PLL a multi-mode divider has to be redesigned in different fabrication processes, which costs more money and consumes more power. Besides, in order to consider both resolution magnification and phase-locked range, it is necessary to use an accumulator that has a great number of bits, which consumes hardware space.
Therefore, it is imperative to provide a non-integer digitally phase-locked loop frequency synthesizer and a loop locking method thereof, which have the advantages of programmability, resisting noise signals, increasing resolution and ease in integration, will not be affected by various factors, such as environment, temperature and voltage shift, and occupies a smaller area as the fabrication process makes progress.